Verilog Tutorial Frame 6

Verilog Tips

Links Mentioned

Tip
Discuss PLDs with others at our discussion group.

In the examples I've used in this tutorial, the Verilog logic maps directly to logic gates, which is fine. However, this isn't always necessary or even desirable. For example, consider the case where you want to display a hex number on a 7 segment display. Sure, you could figure out a solution where each segment is driven by an AND gate and a bunch of inverters. However, it is easier to just explain to the Verilog compiler what you want and let it figure it out:

module led09(D, O, clk);
input [3:0] D;
input clk;
output [6:0] O;
reg [6:0] O;

always @(posedge clk)
case (D)
       0:
          O <= 7'b0111111;
       1:
          O <= 7'b0000110;
       2:
          O <= 7'b1011011;
       3:
          O <= 7'b1001111;
       4:
          O <= 7'b1100110;
       5:
          O <= 7'b1101101;
       6:
          O <= 7'b1111101;
       7:
          O <= 7'b0000111;
       8:
          O <= 7'b1111111;
       9:
          O <= 7'b1101111;
      10:
          O <= 7'b1110111;
      11:
          O <= 7'b1111100;
      12:
          O <= 7'b0111001;
      13:
          O <= 7'b1011110;
      14:
          O <= 7'b1111001;
      15:
          O <= 7'b1110001;
endcase

endmodule

The peculiar notation 7'b0111111 is simply another way of saying 7 bits of binary data. The <= operator is a nonblocking assignment. These cause an assignment to occur without stopping further processing. In this case, you probably don't actually need nonblocking assignments.

Another thing to notice about the code is that the output O is also specified as a reg. This means the output is latched with a flip flop. Also notice that D and O are both actually multiple bit signals.

However, the big point is that we didn't tell Verilog exactly how to build the decoder. We only told it what outputs we wanted to correspond with what inputs. The synthesis tool will take care of the details.

If you have a Verilog module you want to use from a schematic you can use the Create Schematic Symbol process to generate a symbol. If the module has parameters, you can easily change them from the schematic editor. The trick is to right click on the module in the schematic editor and select Object Properties. You can use the New button to create a new attribute:

After you click OK, use the Edit Traits button to set the data type (in this case, an integer):

Then set the following options (be sure to click Verilog under Category):

You can find several useful Verilog resources on the left side of this page. Notice that WebPack (like most if not all synthesis tools) does not support all Verilog constructs. It is important to keep that in mind when working through Verilog tutorials, textbooks, etc.