An Example Project

Links Mentioned

Tip
This tutorial assumes you are using XST, although there are other synthesis tools available.

Here is a simple project to try. If you have a 4MHz clock you want to divide it down to make an LED blink visibly. However, the LED should only blink when two input switches are set to 1. If either switch is set to zero, the LED stays dark.

I'm assuming you've worked the main tutorial so I won't belabor all the WebPack interface details. Here's what your new project dialog should look like (adjusted for the device you are using):

The clkdiv module stays the same. When you create a new Verilog Source, WebPack asks you to fill in the ports. You can fill them in if you like and WebPack will create a skeleton. However, you can also just overwrite the file if you prefer to change them later.

Your top module should look like this:

module top(clk,en,en1,q);
// synthesis attribute LOC clk "P9"
// synthesis attribute LOC en "P70"
// synthesis attribute LOC en1 "P66"
// synthesis attribute LOC q "P35"
input clk;
input en;
input en1;
output q;
wire a1;
wire masteren;
clkdiv #(18) u1(clk,a1);
and(masteren,en,en1);
and(q,a1,masteren);
endmodule

The en and en1 ports are the input switches. Notice that the and primitive can take any number of inputs. The first port is the output and then you just add as many inputs as you like. If you prefer you could have used a single and primitive (and dropped the masteren wire):

and(q,a1,en,en1);

That's it! Just double click on Configure Device, let the entire process run and you are ready to download the program. It's really not that hard.

To make things even easier, while you are editing Verilog source, WebPack makes templates available to you that can help you write certain things. To view these, click Edit | Language Templates and pick the Verilog templates:

Studying these templates can help you create your own code too.