| Constraints | ||
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![]() Sometimes you want to provide a command or a hint to the synthesizer or fitter about your intentions for a certain piece of Verilog code. For example, in a top-level module, you might want specify certain pins should be used to match your development hardware. You can do this with special comments. For example, here is the start of a top level module we will develop shortly: module top(clk,en,en1,q); // synthesis attribute LOC clk "P9" // synthesis attribute LOC en "P70" // synthesis attribute LOC en1 "P66" // synthesis attribute LOC q "P35" input clk; input en; input en1; output q; This uses the LOC constraint to assign pin numbers to the different signals. There are many constraints you can use, but LOC is probably the most common. You can find a complete list in the Xilinx documentation. Of course, you can still use the constraint editor to do the same thing (as we do in the main tutorial). In fact, external constraints will override any you provide in a Verilog module. However, if you are working 100% in Verilog, you may find the comments a handy way to control constraints without having to start the constraint editor or Chip Viewer. If you have to assign a group of bits, you can do that too. For example (notice led, sw, and disp): module top(clk,pb,sw,disp,led,dp); input clk; input pb; input [7:0] sw; output [6:0] disp; output [7:0] led; output dp; // synthesis attribute LOC clk "P9" // synthesis attribute LOC pb "P10" // synthesis attribute LOC led "P35 P36 P37 P39 P40 P41 P43 P44" // synthesis attribute LOC sw "P70 P66 P71 P72 P5 P11 P7 P6" // synthesis attribute LOC disp "P17 P14 P19 P21 P23 P18 P15" // synthesis attribute LOC dp "P24" . . . In some older version, you needed to separate the pins with commas, but recent versions now use the syntax above. If you have trouble, try this format: // synthesis attribute LOC sw "P70","P66","P71","P72","P5","P11","P7","P6" © 2002 by AWC. All Rights Reserved. |