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What if you wanted to change the number of bits used by the divider? Sure, you could manually change 19 to some other number, but that could be tedious. Besides, what if you want one 20 bit divider and one 16 bit divider? Do you need two modules. No. Just make the bits a parameter: module clkdiv(clk,q); input clk; output q; wire iclk; parameter BITS=20; reg [BITS-1:0] COUNT; initial COUNT=0; assign q=COUNT[BITS-1]; BUFG clkbuf(iclk,clk); always @(posedge iclk) begin COUNT = COUNT + 1; end endmodule Now, by default, the bit size is 20 bits. However, each instance can change it in one of two ways. Here is a top module that divides one clock with a 20 bit divider and the other with a 16 bit divider: module top(iclk0, iclk1, led); input iclk0, iclk1; output led; wire q0, q1; clkdiv u1(iclk0,q0); clkdiv #(16) u2(iclk1,q1); and u3(led,q0,q1); endmodule You can probably guess that the #(16) tells clkdiv to set BITS=16 instead of 20 (the default). Of course, u1 could use a #(20) statement just to be explicit, but since we know 20 is the default it isn't necessary. The other way to set the parameter is like this: clkdiv u2(iclk1, q1); defparam u2.BITS = 16; This is more self-documenting, but it is also more to type. © 2002 by AWC. All Rights Reserved. |