Extending CLKDIV

Extending Clkdiv

Links Mentioned

Tip
You should avoid specifying things like BUFG unless absolutely necessary. Adding these to your code makes your modules less portable.

There are several ways to improve the clock divider module developed in the last frame:

module clkdiv(clk,q);
input clk;
output q;
reg [19:0] COUNT;
initial COUNT=0;
assign q=COUNT[19];
always @(posedge clk)
begin
  COUNT = COUNT + 1;
end
endmodule

First, you might want to make sure that the clock uses a global buffer (which improves clock performance). In this case, it really isn't necessary since the synthesis software will guess that you want the clk pin to use a global clock, but it can't hurt. If you were driving something Verilog couldn't guess was a clock you might need to explicitly specify a clock buffer to prevent the synthesis software from trying to use a normal input buffer that (depending on the device you are using) you may not be able to assign to a clock pin.

The trick is to use the Xilinx BUFG component:

module clkdiv(clk,q);
input clk;
output q;
wire iclk;
reg [19:0] COUNT;
initial COUNT=0;
assign q=COUNT[19];
BUFG clkbuf(iclk,clk);
always @(posedge iclk)
begin
   COUNT = COUNT + 1;
end
endmodule

Now the clock runs through a BUFG named clkbuf. This is just like the case where the top module instantiated a clkdiv component, but BUFG is built in. You can find the Xilinx modules in the documentation (see left), but they don't talk too much about the Verilog side of things. That's OK. You can look in your WebPack directory for the verilog/src/unisims directory and see Verilog definitions of the things you can use.