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Tip
You can also use VHDL instead of Verilog. Personally, I find Verilog easier to read and write.

 

Let's try a more sophisticated project that uses some real Verilog. This tutorial doesn't cover Verilog, but you can pick up the flavor of using Verilog and their are plenty of Verilog and VHDL (a similar language) tutorials on the Web.

This project will take a clock input and divide it down so you can count from 0 to 3 on two LEDs. You can use the same circuit used for the half adder, although you don't need the switches.

In addition, you need a clock source. This could be from a function generator or any sort of oscillator circuit (e.g., a 555 or a PIC or Basic Stamp set to generate a frequency output). I used a 50MHz "can" oscillator.

These "cans" require 5V and ground and provide a stable frequency output. The Xilinx device has several special clock pins. Using these pins for clocks helps to ensure that all flip flops will "see" the clock at the same time.

The XC95108 (and the pin-compatible XC9572) has three clock pins: pin 9 (GCK1), pin 10 (GCK2), and pin 12 (GCK3). I connected the oscillator to pin 9. Of course, counting at 50MHz would be faster than the eye can see. You need to divide the clock by some large number.

If you browse the schematic editor's parts lists, you'll see that there are counters, but none large enough to divide down 50MHz reasonably. Of course, you could gang up several. You could also design a large counter using flip flops, but that would be tedious.

A better answer is to describe the counter using a high level language. This is much more efficient than drawing the schematic.

Make a new project. Mine is called blink2. Add a Verilog source. Specify one input named clk and two outputs: q and pulse. The q output will be the divided clock and the pulse output will generate a single pulse every time the division period expires.

Edit the Verilog template to look like this:

The reg keyword makes a "variable" named clkdiv that is 26 bits wide. The q output is set to be the same as bit 25 of this variable. There is also a single bit variable named pulse. When the clock makes a positive edge, the chip will add one to clkdiv and then if bit 25 (and only bit 25) of clkdiv is set, the pulse output will be set to 1.

If you are using a clock slower than 50MHz you'll want to reduce the number of bits. Say you wanted to use an 8 bit counter. Your code would look like this:

You can make a symbol for this clock divider. In the next frame you'll drop this symbol on the schematic.