| GTS and GSR Revisited | ||
| Links Mentioned Links Tip |
![]() Make simpleff look like this again:
This example works out well since the clear line is a natural place to attach GSR for simulation. However, in a more complicated project, this might not be an option. For example, if you use multiple flip flops, each CLR input would need to connect to GSR. Instead, it would be better if you could develop a standard way to handle simulation. That's what we'll do in this frame. What we'll do is create a test schematic that contains the design we want to test as a single block, plus a Verilog module that manipulates GTS and GSR. You can take any design and make it into a single symbol that you can use in other designs. This is useful if you want to make reusable blocks, for example. However, in this case we will use it both to make a reusable block (the GTS and GSR simulation block) and to create a single "device" to simulate. With the simpleff schematic selected in the Project Explorer, select Create Schematic Symbol (under Design Entry Utilities). Now right click in the module view and create a new source. This time, make a new Verilog module named globsim. You'll see this dialog:
Fill the dialog in as shown and click Next then Finish. The resulting module will contain a skeleton: module globsim(GSR,GTS); output GSR; output GTS; endmodule Edit the text so that it looks like this: module globsim(GSR,GTS); output GSR; output GTS; reg GSR; assign glbl.GSR = GSR; reg GTS; assign glbl.GTS = GTS; initial begin GSR = 1; GTS = 1; #100 GSR = 0; GTS = 0; end endmodule This Verilog code tells GSR and GTS to start a 1 and in 100nS, flips then to 0. Now, select globsim.v in the module view and use the Create Schematic Symbol task to make a symbol for this module. Now, you can create a test schematic. Add a new schematic source named simpleffsim. When the schematic editor opens, you'll notice the category display has one category for your current working directory. Select it and you'll see the two symbols you created as components. Drop one of each on the schematic. Then add I/O markers for CLK and Q as before:
Notice you don't have to hook GSR and GTS to anything. Now you can create a test bench for this new schematic. You just have to remember to select simpleff and not simpleffsim when you are ready to actually program the device. Here's the test bench output:
You can simulate this "test" schematic in ModelSim too:
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