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Tip
A functional simulation is more forgiving than a post-fit simulation. For post-fit simulations, the GSR and GTS signals must meet certain timing constraints.

The WebPack tools have a bad rap when it comes to simulation because it has one little quirk when working with clocked logic. The simulation libraries know about two global symbols GSR (the global set/reset signal) and GTS (global tristate signal). Let's see what happens when your design uses these implied signals and you don't handle them.

I've created a new project called simpleff. Here's the schematic:

This should just divide the clock input by two. However, let's try simulating that to see if it works. Create a testbench (named simplefftest).

On the timing screen, you'll see that the TestBencher correctly identified the CLK pin as the clock input. It also put in the values for a 4MHz clock running at 50% duty cycle. For this example, we don't really care what the clock value is, so 4MHz is fine (1/(125E-9 + 125E-9) = 4E6). Click OK.

Right click in the 1000nS slot of the waveform display and select Set End of Test Bench. You don't need to enter any input stimulus since the clock is the only input and it is already set up. Then save the waveform and exit TestBencher. Just ignore the warning about the end of the test bench (press the Ignore button). Then run the Generate Expected Simulation Results task. The result is unspectacular:

This simple circuit doesn't work because the GSR line is not simulated and therefore the chip is held in reset. There are several ways to fix this. Since this is a simple project, the easiest is to just add GSR as an input to the reset line of the flip flop.

Now, if you open the test bench, there is no difference. That's because the test bench doesn't know you've made any changes. So before opening the test bench (or close it if you already opened it) you should synthesize your design. Just select the simpleff schematic and double click the Synthesize workflow entry in the Process View window. Now when you open the test bench it will notice something has changed and will prompt you to refresh the ports. Allow it to refresh and you'll see the GSR trace. Make the GSR trace start at 1 and then go to 0:

Now close the test bench and rerun the Generate Expected Simulation Results process. That's better:

You can do the same trick with GTS, if you need it (this design is not affected by GTS). In the next frame, you'll see a more general solution. Incidentally, the GSR and GTS1 and GTS2 pins are real pins (pins 74, 76, and 77) although you can use them as regular I/O pins if you prefer, so you can actually use GSR and the other special pins in your design for real.