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Tip
This simple project doesn't require a clock, but most projects will.

It is easy to do simple simulations with WebPack. You can automatically generate a test bench, set simulated inputs to your design, and view the outputs. WebPack also includes ModelSim which is very powerful, but harder to use.

To perform a simple test simulation do the following steps:

Right click on the hadd icon and select New Source.

Make a Test Bench Waveform named haddtest.

The next screen will ask what file you want to associate with the waveform. It suggests hadd, and you can just click Next and Finish.

After creating the test bench, you'll see a screen that allows you to select a clock rate. This simple design isn't clocked (it is combinatorial).

The default settings for this screen are usually adequate. When you have a clocked design, you can set the simulated clock frequency using this screen. Press OK. The waveform display initially shows your inputs as zeros. If you click on a part of the waveform, everything from that point forward will turn to a one. Then you can click further down to invert that part of the wave back to 0. By repeating this, you can create any waveform you want (try clicking on the B0 and B1 lines -- it is easier to see than it is to explain). Duplicate the waves shown below.

You can also rearrange the order of the waves by grabbing the labels and dragging them. For this example, the default layout is satisfactory.

Press Save Waveform on the toolbar. The program will probably warn you that you didn't provide input to the end of the simulation. You can allow the simulator to run 1 extra cycle after the end of the input data. You can also right click in the waveform and select Set End of Testbench (indicated by the blue vertical line).

In this case, just set the box to 1 and press OK. Close the TestBench generator and return to the Project Navigator.

You can perform many fancy simulations using ModelSim, but that will have to wait for another tutorial. For now, select the haddtest source and run the Generate Expected Simulation Results command.

You can see that the results are as you'd expect. Because of the initial settings, there is an apparent 50nS delay from the inputs changing to the outputs changing. This isn't an accurate number, however. It was set in the initial test bench screen. You can press the Timing Constraints toolbar button to change this supposed delay. When you close the program, it will ask you if you want to save the waveform. If you pick no, you'll lose your simulation results.

If you want to try ModelSim, close the TestBencher program and return to the Project Navigator. Select the test bench source and run the Simulate Behavioral Verilog Model command. This also simulates without regard to real device characteristics. The Wave window will have the results. However, you will have to zoom out to see the results in a meaningful way (use the Zoom menu).

The TX_FILE and TX_ERROR "waveforms" aren't really waveforms at all. They provide information about the internal workings of the simulator. Obviously, you want the TX_ERROR wave to stay at 0!

The simulator runs for 500nS and stops. You can use Run | Run All to run the entire data set or use one of the other choice in the Run menu to run, for example, 100pS further into the simulation. The advantage to using ModelSim is that you can stop the simulation, manually change input values, and perform some very sophisticated analysis with custom Verilog testbenches.

You can close ModelSim and try running it again with the Simulate Post-Fit Behavioral Model command. Again zoom the wave form out to make it readable. This simulation actually accounts for device characteristics and real-world delays.