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Tip
Assigning I/O and other layout constraints to a chip is sometimes called "floorplanning".

Remember, you can't drop an I/O marker directly on a gate input or output. In the drawing below, for example, you must draw wire "stubs" from the gate outputs so you can drop a marker.

These new markers will have automatically generated names that make no sense. Double click each marker and change the node names to match this drawing:

And you are done! Before you leave this frame, press Tools | Check Schematic check your design. You should get no errors. If you do get errors, fix your problems before you continue. Common errors occur when you fail to connect items, or have multiple connections made incorrectly.

Switch back to the Project Navigator. We need to assign the I/O markers to physical pins (constraints in Xilinx terminology). If you don't care, you can omit this step and let the compiler pick pin numbers for you. However, most often, you have a circuit in mind and you want to fix these I/O markers to particular pins.

For this design I'll use pins 70 and 71 for sum and carry. B0 and B1 will be on pins 61 and 62. Make sure hadd is highlighted in the Sources in Project window. In the lower window click the plus sign next to Design Entry Utilities. Then click the plus sign next to User Constraints. Double click Assign Pins (ChipViewer). This will open the ChipViewer window:

You may need to zoom in (with the + icon on the toolbar), and resize the window to see everything clearly. Also, you'll need to click the plus signs in the Signals column to see all the inputs and outputs.

Just click on an input and then click on the corresponding pin. Repeat for the remaining inputs and outputs. That's it! Use File | Save to save the file, close ChipViewer, and switch back to the Project Navigator.