Starting the Half Adder
Links Mentioned
Xilinx Docs

Xilinx Library Guide
 

Links
AWC PLD Page
 

Tip
A half adder is called a half adder to differentiate it from a full adder. A full adder takes two bits plus a carry input.

Home
Getting Started
Road Map
Half Adder
Adding I/O
Get Ready...
Testing
Testing (pt. 2)
GTS and GSR
Another Project
Another Project (page 2)
Another Project (page 3)
Schematic Tricks
A Real Project
Hardware
Simulation Revisited
Post Fit Sim
Information Please



When you start WebPack Project Manager you'll see a blank work area. The first thing you want to do is create a new project (File | New Project on the menu). You'll see a dialog box:

 

I'll name the new project hadd. The location gets set automatically, although you can change it if you like. For this project, we want the XC9500 family, the XC95108 PC84 device, and as a matter of habit, I select XST Verilog (although for this simple project, EDIF would be OK too). Press OK. NOTE: If you are using our kit, you'll want to use the XC9572 instead of a 95108. That's OK since the 9572 is just a slightly smaller device and this design will hardly use any of the chip.

Next, you'll see several windows at the left side of your screen. The top window shows your design files. The window below this one shows different operations you can perform on the currently selected design file. For this project, we want to draw a schematic. Right click on the hadd entry in the top window:

Select New Source. This brings up a dialog where you can pick what kind of design file you want to create:

Obviously, you want to select "Schematic" as the document type. I named the file hadd, since this will be the top-level design file. Press Next. You'll see a confirmation screen; just press Finish. This will bring up the schematic editor, which is a different program.

Now you are ready to draw the schematic. On the right hand side of the schematic editor, you'll see a window that contains categories and symbols. The symbols we want are in the Logic category and are named xor2 and and2 (a two input xor and an and gate, as you might guess). Select each gate, move the mouse over the schematic area, and click to drop the gate. Then you can use the Add Wire command (or the Add Wire tool button near the top of the window) to draw the connections. Your final result should look like this:

Notice that the outputs have short wire stubs drawn from them. This is necessary since you can't put an I/O marker directly on a gate output. You'll add I/O markers to the wire stubs in the next frame.

When you are drawing a wire, you can double click to end the wire without dropping the tool. This is especially handy when drawing the wires to nowhere.

Incidentally, you can find Xilinx's complete documentation (some of which doesn't apply to the Web Pack) at http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm.

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