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Tip
Experiment with different options may allows you get better speed or fit more on a device.

After you've done all this work, you might want to know some details about what's going on. After all, the Xilinx software did something to cram your circuit on the IC. What's going on?

Armed with the complete design, select bigout.sch in the Module View of the sources window. Here are a few useful ways to view the IC:

View Verilog Functional Model (under Design Entry Utilities)
This option lets you see your design in Verilog. Many people prefer to create complex circuits using Verilog (or VHDL) instead of schematics.

View Synthesis Report (under Synthesis)
This shows you the report from the synthesis step. This step is where your logic is compiled into a form that is ready to be placed on the chip, but before the actual fit of the design into silicon. If this were a C compiler, this step would be like a compile but before the link step. You can alter many options the synthesizer uses by right clicking on Synthesis and selecting properties:

Of particular interest: you can ask the compiler to optimize for speed or to conserve chip area. You can also ask the compiler to spend more or less time trying to optimize.

Fitter Report (under Implement Design, Fit)
This report tells you many details about the layout of the chip, how much of the chip is in use, and the internal routing.

You can also view the fit data graphically using ChipViewer by selecting the option just below this one in the process window. There are many fit options you can set by right clicking on Fit and selecting properties:

A very useful option (on the Basic tab) allows you to set unused pins to output 0s. You can also set the fitter to reduce the chip's speed to save power consumption.

Timing Report (under Implement Design, Generate Timing)
This report tells you information about the delays in the chip and the maximum clock frequency which is what you are usually interested in. For example, the bigout design has a maximum clock frequency of 83.3MHz (12nS period). If you need more information, right click on Generate Timing, select properties, and change the default reporting level. For even more details you can run the Timing Analyzer (Analyze Post Fit Static Timing).

When you are happy with your project (or reasonably so) you might want to take a snapshot or archive it (these choices are on the Project menu). An archive makes a ZIP file with the current files whereas a snapshot stores the files in a directory and allows you to restore to that point easily. This is a good idea if you are about to make big changes, obviously.

This concludes this tutorial. Of course, there is much more to learn, but you now have the basic tools to design, simulate, and implement CPLD designs.