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The simulation you just performed is behavioral. It makes certain generalized assumptions about your circuit that may not be true when you actually burn it into the chip. This includes things like setup and hold times and also propagation delays.

These subtle things can make your real circuit behave differently from your design. They also make a post fit simulation harder to successfully run than a behavioral one.

Since a post fit simulation (PFS) compiles your code for silicon, you can't use crutches like the GLOBSIM block -- it doesn't really exist. That means you'll need to make a new test bench attached to the normal schematic instead of the one with GLOBSIM added. I called my test bench fitsimbigout.tbw.

The timing parameters are crucial to success. If you don't set them correctly the simulation will generate errors when you violate setup and hold timing constraints. In most projects, of course, you want to match the clock source. Here, however, we are faking the clock from the Basic Stamp so we can't match it exactly. The important thing is when the external device will set the inputs and when it will sample the outputs along with the clock's frequency. For the Stamp this is quite slow (compared to the 100s of MHz these chips can handle).

For this simulation I'll set up to be much faster than the Stamp on the theory that we can always run slower. Here's the constraints:

This represents a clock with a period of 1uS (1000nS) or 1MHz. The inputs will be stable for 100nS before the clock edge and sampling occurs 100nS after the clock edge. Now you simply need to program a test case as before.

You need to give the chip time to reset (this is a real simulation so even the time the chip is waking up is simulated). Here's my test data (click to enlarge):

OK, so now you can just go to the process window and run Simulate Post Fit Verilog Model, right? Not so fast! The problem is, GSR is still not set correctly and by default the simulator will try to run 1000pS or so when you first start it. We need to stop it from doing that.

The trick is to right click on Simulate Post Fit Verilog Model in the process window and select Properties:

Set the Simulation Run Time to 0. You can also set the Simulation Mode to see typical, minimum, or maximum delay. Maximum delay is safest -- if your design works on this setting it should be fine on a real device.

Now run Simulate Post Fit Verilog Model. This opens the ModelSim simulator. You may have notice that when you perform commands with the mouse in ModelSim it really just feeds text commands to the command line. That means you can make .DO files that contain command sequences and that's what I've done to simplify starting the chip's GSR line. Create a file called simsetup.do using Notepad or any other text editor. It should contain the following:

This just lets the chip run for 500pS and then pulses all the global signals for 5uS. Save the file in your project directory. Then you can execute the commands automatically. One way is to go to the ModelSim command line and enter:

Or, if you are more mouse-oriented than I am, you can use the Macro | Execute Macro menu command. Pick simsetup.do from the file dialog and you are all set.

After the commands are complete you can enter:

run -all

Or pick Run | Run -all from the menu. I suppose you could add the command to the end of the do file, but I don't. The simulation will run to completion (the point you set when you created the test bench). The result should be gratifying (after you fiddle with the zoom factor):

Congratulations! You've done a successful post-fit simulation. If you had failed to get the timing constraints correct, you'll get unknowns in the results and errors in the main simulation window. For example, I went back to the test bench and set the timing constraints so that the input hold and sample times were 5nS instead of 100. Here's the result:

Failing to initialize GSR looks like this:

Notice that everything just sits at zero no matter what. That's a good sign you didn't go through a reset.

In a normal project, this is when you'd go ahead and burn a chip and expect it to work. Of course, I wanted you to see what the chip does first, so I've already covered that step a few frames back.

In the next frame, we'll look at how to find out what the tools have done for you.