| Simulations Revisited | ||
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Tip |
![]() You've probably already built the Bigout project and have LEDs merrily blinking and winking. However, in real life you probably want to simulate before you start burning silicon. However, if you try simulating the design as-is nothing happens. Why? It's that pesky GSR global signal again! There are a variety of ways you can handle this. I decided to add the GLOBSIM Verilog block again. Remember GLOBSIM? I use it to strobe all the global signals on startup (even the ones I'm not really using). You can copy it from a previous project or just add a new Verilog source that contains the following: module globsim(PRLD, GTS, GSR, GR); output PRLD; output GTS; output GSR; output GR; reg PRLD; reg GTS; reg GSR; reg GR; assign glbl.PRLD = PRLD; assign glbl.GTS = GTS; assign glbl.GR = GR; assign glbl.GSR = GSR; initial begin PRLD=1; GTS=1; GR=1; GSR=1; #100 PRLD = 0; GTS=0; GR=0; GSR=0; end endmodule Then you can create a symbol for bigout.sch and globsim.v (use the Create Schematic Symbol process under Design Entry Utilities). Then create a test schematic that contains the bigout.sch symbol and the globsim symbol. Bring all the I/O pins on bigout to I/O pins on the new schematic:
Finally, create a testbench named SIMBIGOUT using the Test Bench Waveform source type. The Stamp doesn't constantly clock the clock, so using a Master Clock setup isn't a perfect simulation, it works and is easier to set up since you are using clocked logic:
Now you can set up a test case. Here's a simple one with the results of the Generate Expected Simulation Results process (click on the thumbnail to enlarge): You might want to try the Simulate Behavioral Verilog Model to run ModelSim directly. This will produce the same results, but give you control during the simulation. You can't, however, run the Simulate Post-Fit Verilog Model without some changes. There are several reasons why this is true and we'll look at them in the next frame (which is coming soon). © 2002 by AWC. All Rights Reserved. |