Xilinx Library Guide

Links
AWC PLD Page
 

Tip
Bus connectors are great, but if your schematic is very complex, consider breaking it into sub modules. Just draw a part of the circuit on one schematic, create a symbol from that schematic, and then use the new symbol in another schematic.

As your schematics get more complicated, you may want to partition them into modules. Each module is a separate schematic. You can then create a schematic symbol for the module and use it in a higher level schematic. You can have many levels of schematics, each building on lower level modules.

In addition, you can create busses to help organize related wires on the schematic. Although it is overkill on the counter project, it is easy to see how this can work on this simple schematic.

First, delete the wires that connect the inverters and the counter:

Next, draw a wire from the general vicinity of the Q0 and Q1 outputs to the general vicinity of the inverters. Don't connect it to anything:

n

Now, the Add | Net Name menu item to name the unattached wire Q(1:0). You specify the name in the tool bar and then click on the wire. After you name the wire, it will become thicker (because you've specified more than one wire). Select Add | Bus Tap from the menu. You can rotate the bus tap using the tool bar. You'll add four taps. You want to connect the wide ends of the taps to the bus you've created and the thin ends should be in a line with the Q0 and Q1 outputs and the two inverters.

If there are gaps between the thin end of the tap and the wires leading to the devices, use the wire tool to fill them in. You can't connect the tap directly to the device. There must be at least a small wire connecting them.

Next, you'll name the connecting wires. You do this the same way you named the bus. However, the wires will only have a single number in the parenthesis (so Q(0) is one wire, for example):

If you can't get the name to "take" you are probably clicking on the tap or the device's pin stub instead of the wire segment. You should be able to click the check mark icon now and get a clean bill of health. This schematic is functionally the same as before, but now both Q signals travel on one bus. Internally, this is unimportant, but it makes your schematic neater. Of course, you can carry many signals in one bus. For example, an 8 bit data bus might be DB(7:0).

You can also name a bus with unrelated signals separated by commas. For example, you could name the bus "Q1,Q0" and then name the wires Q1 (instead of Q(1)) and Q0. You could as easily make a bus that contained signals named Read, Write, and Enable. Another bus with five signals might be named Q(3:0),Clock.

Another twist, is that you can make busses that tap other busses. For example:

There are other items of interest on the Tools menu. Selecting Query from the Tools menu switches the schematic editor to query mode. Clicking on any item in the schematic will cause the editor to display information about that item.

If you start with an empty schematic, you can use Tools | Create IOMarkers to create I/O markers automatically. You can then connect wires to these markers and connect them to other components.

You can even make pin assignments from the schematic editor. The LOC constraint lets you assign a pin number to a pad. Simply right click on the pad and pick Object Properties. Use the New button to add a LOC attribute and make its value the pin number you want (precede pin numbers with P so pin 80 is P80):

One more item of interest: You can find a very complete manual online at http://toolbox.xilinx.com/docsan/xilinx4/manuals.htm. Some of this doesn't apply to the WebPack program. However, the Libraries Guide is especially useful.

Watch for more frames soon!