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Tip
Verilog is very much like C. VHDL is more like Ada.

If you want to simulate this project, you should reduce the count in the Verilog clkdiv component. Edit the clkdiv.v source so that it looks like this:

module clkdiv(clk,q,pulse);
input clk;
output q;
output pulse;
// reg [25:0] clkdiv;
// assign q=clkdiv[25];
// this is just for simulation
reg [3:0] clkdiv;
assign q=clkdiv[3];


reg pulse;

always @(posedge clk)
begin
clkdiv=clkdiv+1;
// pulse = (clkdiv==26'b10000000000000000000000000)?1:0;
// for simulation
pulse = (clkdiv==4'b1000)?1:0;
end

The // characters are comments, and leaving the real code in view will help prevent confusion. Next, copy the globsim.v file from the simpleff project directory into your working directory for this project. In case you forgot, here's globsim.v:

module globsim(GSR,GTS);
output GSR;
output GTS;
reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GSR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end
endmodule

Right click in the module view and select Add Source. Pick globsim.v from the file open dialog that appears. From the process view select Create Schematic Symbol. Then open up the main schematic and drop a globsim object. Since this is a simple project, I'll just simulate and then when I'm done I'll just delete the globsim object, restore the clkdiv component to its original state and rebuild everything.

Now everything is in place for creating a test bench. Just right click in the module view, select New Source, and create a test bench called blink2test. Set the end of the test bench at least 100 cycles past the beginning.

Run the Generate Expected Simulation Results process. You'll find a disappointing result:

LEDA and LEDB are in the Hi-Z state. Interestingly, the design will actually work if you program a chip. The problem is, there is no initial state for clkdiv. Since its state is unknown, the simulator assumes that adding one to it, or any other operation, will result in an unknown state. However, the real hardware will work, because it doesn't really matter what clkdiv starts at. Besides, the GSR pulse should reset all the flip flops (unless you explicitly preset them).

A simple change to the Verilog file (shown in red below) will allow you to set an initial condition for simulation:

module clkdiv(clk,q,pulse);
input clk;
output q;
output pulse;
// reg [25:0] clkdiv;
// assign q=clkdiv[25];
// this is just for simulation
reg [3:0] clkdiv;
assign q=clkdiv[3];

reg pulse;

initial      //***** changed
clkdiv=0;    //***** changed

always @(posedge clk)
begin
clkdiv=clkdiv+1;
// pulse = (clkdiv==26'b10000000000000000000000000)?1:0;
// for simulation
pulse = (clkdiv==4'b1000)?1:0;
end


endmodule

That's better!

The initial statement is ignored when synthesizing the design, but works fine for simulation. When you synthesize the design you'll get a warning that the initial statement is ignored.

Now you can simulate all you want. When you are ready to burn the chip, remove the globsim block from the schematic, restore the Verilog file to its original condition (comment out the simulation-specific lines and uncomment the original lines). Then you can proceed as before -- create a device file and use iMPACT to program the chip.

Watch for more frames soon!