Links
AWC PLD Page
 

Tip
The two bit counter happens to be in the libraries. However, if it were not, it would probably be easier to create it in Verilog. LogixBlox allows you to create custom components from a template (so you could ask it to make you a, say, 34 bit counter). However, LogixBlox isn't part of the free WebPack software.

 

Armed with the clock divider, it is easy to draw the following schematic:

The inverters are not strictly necessary and you may omit them if you prefer. With the inverters the LEDs will be off for a 1 and on for a zero (which works out well if you are driving some other load through a transistor). Of course, it is simple to add or delete them as you see fit. The CB2CE block is a 2 bit counter (see the library documentation online).

Because of the special clock pins, it is a good idea if all the clocks in your circuit connect to the same pin. So instead of making the clock divider connect to the counter's clock, it feeds the counter's clock enable pin (CE). This allows the counter to ignore the incoming clocks except when the CE input is true.

Use ChipViewer to set the CLK pin to pin 9 and the LEDs to pins 61 and 62. The problem with this circuit is trying to simulate it. Waiting for the divider to count down would require a very lengthy simulation. You can, however, change the component (just for simulation purposes) to count down, say 4 or 8 clocks). You'll see how in the next frame.