1	Programmable Logic My Roadmap to PLDs and FPGAs by Al Williams WD5GNR
2	What’s Programmable Logic? Chips that can implement complex logic function Consist of I/O pins, logic blocks, and a programmable interconnect By changing connections, you can make many different circuits
3	Why not a Microprocessor? Unlike a Microprocessor, a PLD implements real logic gates PLDs can operate very fast PLDs can do more than one thing at a time – a single micro can only pretend to do more than one thing at a time
4	Types of PLDs PLD – Programmable Logic Device (inexpensive, small, unobtainable today) CPLD – Complex PLD (more gates than a PLD) FPGA – Field Programmable Gate Array (many more gates, much more expensive; some > $500/each) I call them all PLDs for simplicity
5	Problems PLDs typically are in PLCC or other packages difficult for hobby work Many PLDs work on 3.3V or less to reduce power consumption (but most can work with 5V I/O) Steep learning curve for software – many choices from many vendors
6	Basic Design Flow Describe your desired circuit using a software tool Compile your circuit Simulate the circuit on the PC to see if behavior is correct Program chip using special printer port cable
7	Circuit Description Usually at least four ways to describe your circuit Schematic drawing (vendor specific) VHDL language (standard) Verilog language (standard) State machine or waveform (vendor specific) Some vendors supply proprietary languages also
8	Vendors Altera – Good tools (but maybe too many of them); Free tool works well Xilinx – Easy to buy through DigiKey; Free tool is OK but not as well-integrated as Altera Atmel – Small DIP CPLDs available; free software appears to be low-end Many others that I don’t know much about
9	Altera This demo uses an Altera MAX3000A device and the MAX+PLUS II Baseline software (free from Altera) It also uses the Altera free version of Leonardo Spectrum The MAX3000A can implement about 2500 logic gates – this is not very big compared to many FPGAs
10	The Plan The idea is to use the MAX3000A as a timer It will count minutes and seconds on the LED display The test board has a 53.125MHz clock (loafing for the MAX3000A) and LED digits so this is a software-only project
11	Schematic
12	Notes on Schematic The thick lines are busses, so LEDA[6..0] is actually 7 wires A 7449 is a standard TTL LED driver and is part of the library supplied with the software The 7449 drives the LEDs the wrong way, so I “flipped” them in software (note the circles on the outputs) Other than the 7449 the parts are custom-made
13	A Walking LED The decimal points “walk” once per second The next slide shows the seq4 custom component that does this The counter and decoder were built with a Wizard that customizes stock parts supplied with the software
14	SEQ4
15	The Wizard
16	Decoding Top Digits The top digits only range from 0 to 5 so a whole 7449 is not required However, the compiler will optimize unused logic out of the design On the other hand, I decided to try writing my own 0-5 decoder using Verilog (the LED05 component)
17	LED05 /* BCD 0-5 -> LCD -- Williams */ module led05(D, O); input [2:0] D; output [6:0] O; reg [6:0] O; always @(D) case (D) 0: O <= 7'b0111111; 1: O <= 7'b0000110; 2: O <= 7'b1011011; 3: O <= 7'b1001111; 4: O <= 7'b1100110; 5: O <= 7'b1101101; default : O <= 7'b0; endcase Endmodule
18	Schematics vs Verilog You could define the same thing as a schematic, but sometimes it is easier to describe what you want VHDL is another way to do this Verilog is C-like; VHDL is Ada-like The free tool doesn’t directly compile Verilog or VHDL but the Leonardo Spectrum program does
19	The timebase Component /* Time Base component by Al Williams made for Post-It board with 53.125 MHz clock */ module timebase(sys_clk,sys_rst_bar,onesec_clk); input sys_clk; input sys_rst_bar; output onesec_clk; reg [25:0] sec_clk; reg clkstate; parameter CLKBASE=53125000; assign onesec_clk = clkstate; always @(posedge sys_clk or negedge sys_rst_bar) if (~sys_rst_bar) begin sec_clk<=0; end else if (sec_clk==CLKBASE) begin clkstate <= 1; sec_clk<=0; end else begin clkstate <= 0; sec_clk <= sec_clk+1; end Endmodule
20	Simulation You can build test cases and simulate them to view the results I changed the timebase component to pulse on 5 clocks to make the simulation manageable
21	Results
22	What Could You Do? This uses about 58% of this chip’s resources A scope trigger could monitor complex logic conditions and trigger a scope A keyer Frequency counter Anywhere you need fast logic
23	Links Vendors http://www.altera.com http://www.xilinx.com Tutorials http://www.aldec.com/Free/ Evita_Verilog.exe General http://www.optimagic.com/