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Tip
You can add the DIA source to your project also for management purposes, although this is not strictly necessary.

Once you've finished with StateCad you can return to the main navigator. Interestingly, creating the new source did not actually add it to the list and it certainly didn't add the Verilog source. So add these existing sources (the names will be VCRFSM.DIA and VCRFSM.v, in this case).

From this point, the state machine is just another chunk of Verilog code. You could instantiate it in other Verilog code, or create a schematic symbol for it. Go ahead and create a schematic symbol (in the Design Entry Utilities process).

Now you can add a schematic and place the symbol on it.

Just to test things out, add a wire and an I/O marker to each pin. Just name the node the same as pin name in the symbol.

It is easy to build a test bench, make up some test data, and get some simulation results. Again, if you aren't comfortable with simulation, you should work the main WebPack tutorial.

Notice this behaves like you'd expect. Although it seemed involved going through the design step by step, consider this: at no time did you have to consider flip flops, clock enables, or any other technical details. You simply drew states, conditions, and outputs. StateCad did all the work.

Do you remember that I mentioned I left out a state transition? Did you find it? There is no way to turn the VCR off unless you are in play or record mode!

Here are some exercises to try on your own: