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Tip
You can run the optimization wizard separately if you want to optimize a manually entered state machine.

Once you've done the basic set up, you'll see the screen above. Press Next, of course.

I'll pick CPLD since I'm using an XC95108.

For most cases, you'll want to select Speed optimization. This uses registered (flip flop) outputs. However, you can use combinatorial logic to save space in the device, but at the expense of propagation delays in the output.

We specified @ELSE in the transitions to prevent states that have no next state in some conditions (since the @ELSE will match if nothing else does). However, you can ask StateCad to do this for you automatically. However, catching all these possible states can increase device utilization. Still, if you have the room, it makes for a more robust state machine. In this case, I'm picking implied else.

You'll usually leave this screen at its default values unless you are trying to save space or manage signal loading.

StateCAD will generate HDL for your state machine, so I selected Verilog. I also need to pick XST since that is what I'll use in the project:

The rest is housekeeping:

The Wizard now jumps the gun trying to analyze the machine before we've really done anything:

I prefer not to do much at this point. However, you can delete the A, B, Up, and Down variables when prompted. Just blow through the errors (or cancel). You'll eventually wind up at a window with Verilog code. Close that since it isn't complete yet and proceed to the next frame.