Introducing Verilog (with Xilinx WebPack)

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Although it is seductive to use schematic entry when designing programmable logic, it quickly becomes apparent that really complex designs are very difficult to enter. For example, suppose you have a 1MHz clock and you'd like to divide it by 1,048,576 (that's 2 to the 20th power). You'll wind up drawing 20 flip flops. Not only is that a lot of flip flops, but what happens if you change the clock to, say, 10MHz. Now you need to add many more flip flops to get the same output frequency. Reduce the the clock rate and you have to take flip flops away.

Verilog is a C-like language that allows you to describe circuitry and solves many of the problems involved with schematic entry. For example, here is a simple clock divider:

```module clkdiv(clk,q);
input clk;
output q;
reg [19:0] COUNT;
initial COUNT=0;
assign q=COUNT[19];
always @(posedge clk)
begin
COUNT = COUNT + 1;
end
endmodule```

You can probably figure most of this out. This tutorial won't completely cover Verilog (see the link to the left if you want a good general Verilog tutorial).  However, let's look at this module and see what we can learn:

 The module statement indicates that this module or component is named clkdiv. It has two ports: clk and q. The next two lines (input, output) specify that clk is an input port and q is an output port. The line that begins with reg specifies a "memory" (this will wind up being a flip flop). Actually, since this specifies an array of regs, it will result in 20 flip flops (0 to 19). Collectively these will be known as COUNT. The initial line sets up COUNT=0. The synthesizer won't pay this any attention, but for simulation it is useful. The assign line set up a continuous assignment. Every time COUNT[19] (the most significant bit) changes, the output port q will also change to match. The always line tells Verilog to do the following things whenever it sees a positive edge on the clk input. The body of the always adds one to count.

That's it. You just defined a 20 bit counter in Verilog. You can create a schematic symbol and use it in a schematic, if you like. Alternately  you can use it in another Verilog module. For example:

```module top(iclk, led);
input iclk;
output led;
clkdiv u1(iclk,led);
endmodule```

This creates a module named top that contains a clkdiv named u1. This example is pretty boring, but imagine that you had two clocks that you wanted to divide. The output should be the AND of both divided outputs. You could write:

```module top(iclk0, iclk1, led);
input iclk0, iclk1;
output led;
wire q0, q1;
clkdiv u1(iclk0,q0);
clkdiv u2(iclk1,q1);
and u3(led,q0,q1);
endmodule```

The and is a primitive part of Verilog, so you don't actually have to name it. That is, you could write:

```and (led,q0,q1);
```

A wire just provides a connection between things (the clkdiv components and the and gate in this case). Notice that there are two clkdiv instances. They behave the same but they are completely separate. Think about a real hardware design. You can put two ICs on your board that work the same, but they are separate. That's how u1 and u2 behave in the above example.